1. Field of the Invention
The present invention relates to a process for the simultaneous production of self-aligned bipolar transistors and complementary CMOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones, the n-zones forming the collectors of the transistors.
2. Description of the Prior Art
In highly integrated circuits, the integration of CMOS and bipolar transistors on a common substrate is highly advantageous with regard to system speed because gate delay time losses on lines or other capacitively loaded elements such as outputs can be greatly reduced by bipolar driving transistors. However, this is only possible when the intrinsic switching time of the bipolar transistors is comparable with that of the CMOS transistors and that the yield of the total process is not degraded to a large extent by the additional process steps which are required for the production of the bipolar transistors.
In order to reduce the collector resistance, known processes for the integration of bipolar and CMOS transistors use a buried collector with subsequent epitaxy. A process of this type is, for example, disclosed in the paper by H. Higuchi et al entitled "Performance and structures of scaled down bipolar devices merged with CMOSFETS" in the IEDM Technical Digest (1984), pages 694 to 697. However, these process steps frequently result in relatively high densities of imperfections of the crystal and therefore restrict the yield and thus the degree of integration of the circuit.
On the other hand, if the buried collector is omitted as disclosed by a paper by F. Walczyk and J. Rubinstein entitled "A merged CMOS/BIPOLAR VLSI-Process" appearing in IEDM, Vol. 83, Technical Digest (1983), pages 59 to 62, bipolar transistors with inefficient intrinsic switching times and lowered current efficiencies are obtained through the use of conventional manufacturing steps such as using arsenic-implanted emitters which are aligned relative to the base contact zone.
A considerable improvement is achieved in this respect by means of coupling bipolar CMOS processes with self-aligned bipolar transistors as described, for example, in a paper by A. R. Alvarez appearing in IEDM, Vol. 84, Technical Digest (1984), pages 761 to 764. Previously known processes of this type still produce relatively high base resistances and large lateral distances between the emitter and collector, as a result of which the switching velocities and current efficiencies of the bipolar transistors which are obtained are likewise limited.